1. Field of the Invention
The present invention relates to a method of verifying a semiconductor integrated circuit apparatus, which can sufficiently evaluate a reliability of a non-destructive fuse module after it is assembled, and a semiconductor integrated circuit apparatus.
2. Description of the Related Art
Conventionally, in a semiconductor integrated circuit in which a memory circuit or a semiconductor memory such as RAM (Random Access Memory) and the like is built in, a redundancy circuit provided with an address setting circuit for storing a spare memory row and memory line and a defective address and the like is installed in order to improve a yield by relieving a defect bit (a defective memory cell) included in a memory array.
A method of using a fuse that can be programmed by carrying out a physical destruction through a laser and the like is typically done in setting a defective address in such a redundancy circuit. In a relieving method of cutting away the fuse through the above-mentioned laser, storing a defective address information, comparing with an input address and replacing with a spare memory line or a spare memory row, the fuse must be cut away before a memory chip is sealed in a package. For this reason, it is impossible to relieve a defect induced after the memory chip is sealed in the package. This results in a trouble that a sufficient improvement of a yield can not be attained.
So, a technique is proposed for installing a non-volatile memory such as EEPROM (Electrical Erasable Programmable Read Only Memory) and EPROM (Electrical Programmable Read Only Memory) in a chip of DRAM (Dynamic Random Access Memory) and storing a defective address information as a non-destructive fuse.
If such a relieving method is used, the defective address information can be written to the non-volatile memory even after the chip is sealed in the package. Thus, the defect induced after the chip is sealed in the packaged can be relieved to thereby improve the yield.
There is the technique for improving the yield by mounting the fuse in order to relieve the defect bit after the assembly (after it is sealed in the package) as mentioned above. FIG. 1 shows various fuse methods that have been conventionally put to practical use.
In a case of DRAM, the restriction of a product specification (a package arrangement and the like) is severer than that of a custom product such as a mixture memory and the like. It is difficult to additionally mount a new outer terminal.
So, the non-volatile memory (EPROM) may be employed as a reliable fuse after it is assembled, in which a voltage that can be boosted in a chip can be used.
As shown in FIG. 1, the non-volatile memory has the problem of the reliability as compared with the conventional destructive fuse. However, the problem of the reliability is at the ignorable level in a process in which a thickness of a gate oxide film is thick (a process of 13 nm or more and 0.8 μm).
However, if EPROM is used, it is expected that the thinner thickness of the gate oxide film (for example, 8 nm or less) associated with a higher integration and a lower voltage causes the deterioration in an accumulated charge retaining property, which results in a problem of a reliability reservation.
A method of verifying a semiconductor integrated circuit apparatus, which can sufficiently evaluate a reliability of a non-destructive fuse module after it is assembled, and a semiconductor integrated circuit apparatus are desired.
A method of verifying a semiconductor integrated circuit apparatus, which can sufficiently evaluate a reliability of a non-destructive fuse module after it is assembled without increasing a circuit area, and a semiconductor integrated circuit apparatus are desired.
A method of verifying a semiconductor integrated circuit apparatus, which can sufficiently evaluate a reliability of a non-destructive fuse module after it is assembled in a short evaluation time, and a semiconductor integrated circuit apparatus are desired.
A method of verifying a semiconductor integrated circuit apparatus, which can sufficiently evaluate a reliability of a non-destructive fuse module after it is assembled, and a semiconductor integrated circuit apparatus are especially desired in DRAM in which EPROM (CMOS Process Compatible ie-Flash (inverse gate electrode Flash)) that can be manufactured by using a standard CMOS manufacturing process in its original state is used as a reliving circuit, which will be describe later.
By the way, Japanese Laid Open Patent Application (JP-A-2001-229690) discloses the following semiconductor integrated circuit apparatus. That is, in the semiconductor integrated circuit apparatus, an address to relieve a defect of a memory array in a semiconductor device or a trimming information is stored with a nonvolatile memory element using as a floating electrode a polycrystalline silicon layer of a first layer which can be formed by a CMOS device manufacturing process.